As the degree of integration of VLSI circuits continues to increase, there exists a correspondingly increasing need for fast and reliable methods for testing such circuits. It has been estimated that costs associated with integrated circuit chip testing increase in proportion to the square of the number of devices on the chip. Accordingly, an easily-implemented, fast, and reliable chip testing method is needed.
A known and commonly used technique for testing integrated circuit chips is the boundary scan method, in which a boundary-scan cell is provided adjacent to each pin of an integrated circuit. A boundary scan cell typically includes one or more flip-flops and allows input test data to be supplied to, or output test data to be sampled from, the integrated circuit. The boundary scan cells for each pin of a chip (or from each pin of a plurality of interconnected chips) are connected to form one or more shift registers. FIG. 1 shows an exemplary boundary scan cell. The boundary scan cell includes multiplexers 2 and 4, and flip-flop elements 6 and 8. Data, in the form of test data or instructions, is input to the first inputs of multiplexers 2 and 4 on line NDI, while the output of a previous boundary scan cell is input to the second input of multiplexer 2 on line SDI. The output of multiplexer 2 is determined by a control signal on line SHIFT/LOAD, and the output of multiplexer 4 is determined by a control signal on line MODE. When a LOAD signal is input to multiplexer 2 on line SHIFT/LOAD, flip-flop 6 samples the data on line NDI. When a SHIFT signal is input to multiplexer 2 on line SHIFT/LOAD, the flip-flop 6 samples the output of the previous scan cell. The data sampled by flip-flop 6 may be serially passed through to a successive boundary scan cell via scan data out line SDO, or may be supplied to flip-flop 8. Flip-flop 8 is an intermediate storage element which samples and stores a value for use in a future test. Multiplexer 4 receives normal data on line NDI at one input, and receives test data stored in flip-flop 8 at a second input. Multiplexer 4 outputs data on line NDO under the control of the MODE signal. Thus, if scan cells are each connected to respective data pins of an integrated circuit, test data stored in the flip-flop 8 of each scan cell can be supplied to the data pins under the control of the MODE signal. Flip-flops 6 and 8 operate according to separate clock signals A and B to enable flip-flop 8 to source the output of the boundary scan cell while new data is input to flip-flop 6.
Referring now to FIG. 2, an arrangement of boundary scan cells around a group of interconnected integrated circuits on a circuit board is shown. Collectively, the boundary scan cells around each integrated circuit form a shift register. This arrangement allows the interconnections between the circuit components in each of the integrated circuits to be tested by shifting test data into all of the boundary scan cells associated with integrated circuit output pins and loading input test data in parallel through the component interconnections into the cells associated with integrated circuit input pins. This arrangement also allows the integrated circuits on the circuit board to be tested by isolating the internal logic circuitry of each chip from the surrounding circuit elements while an internal self-test is performed. The boundary scan cell method also permits a limited slow-speed static test of the internal logic circuitry of a chip by allowing test data to be input to the chip and the chip output data analyzed. Because the boundary scan register permits parallel loading of cells at both the input and output pins of an integrated circuit and permits the shifting out of the results, the register effectively samples data flowing through a component without interfering with the operation of the component. While boundary scan cells offer numerous benefits, a functional test of the operation of the complete system of interconnected integrated circuits requires separate automatic test equipment (ATE) or a system-level self test.
Additionally, thorough testing of the internal functions of each integrated circuit is typically not feasible using only this test technique.
A built-in self test (BIST) architecture typically includes a pattern or operand generator for producing test operands, each of which is applied to the internal logic circuitry of the integrated circuit. The results of each test operand are compressed into a "signature" which is compared to predetermined signatures to detect faults. BIST architecture is advantageous because the test circuitry is fabricated on the chip with the main logic functions, while having a minimal impact on the main logic functions. Further, since the test results are processed by BIST circuitry, the number of tasks which must be performed by external components is reduced, and maintenance software is simplified. BIST also allows for testing at full system clock rates, significantly reducing test time. BIST further allows for testing any number of different types of circuits, independent of specific chip logic functions, at the wafer, chip, or system levels, both before and after assembly into a computer.
However, known BIST architectures have limitations. In particular, BIST architectures require a means for selecting a system clock for normal operations and a test clock for test operations. In typical BIST architectures, a clock multiplexer is provided in each integrated circuit having a BIST capability. Examples of such architectures include U.S. Pat. No. 4,701,920 to Resnick et al. and U.S. Pat. No. 5,138,619 to Fasang et al. In such an arrangement, there are significant and variable delays in the clock distribution circuitry. Because different clock multiplexers are used for each integrated circuit in a system, the clock signals supplied to the different circuits may have varying phases (skew). Further, many known BIST architectures include customized interfaces, which often require an increase in the number of input or output pins needed to fabricate the integrated circuit.
It would be advantageous for a BIST architecture to include an industry standardized, low pin-count interface. It would also be advantageous for a BIST architecture to allow the testing using either known, externally supplied test data or pseudo-random test data patterns generated on the chip. It would further be advantageous for a BIST architecture to eliminate the need for an on-chip clock multiplexer to allow the main integrated circuits to operate at a high speed, while allowing the test circuitry to operate at a lower speed, and avoiding significant and variable clock delays and skews.